MC68HC708MP16 Datasheet, PDF (121/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.6.3 PLL Programming Register
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address: $FE0D
Bit 7
Read:
MUL7
Write:
Reset: 0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
VRS5
1
Figure 8-7. PLL Programming Register (PPG)
Bit 0
VRS4
0
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See 8.4.2.1 PLL Circuits and
8.4.2.4 Programming the PLL.) A value of $0 in the multiplier select
bits configures the modulo feedback divider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
121