MC68HC708MP16 Datasheet, PDF (295/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface Module (SCI)
PTF4/RxD
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
LSB
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
Figure 14-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 14-1 summarizes the results of
the start bit verification samples.
Table 14-1. Start Bit Verification
RT3, RT5, and RT7
Samples
000
001
010
011
100
101
110
111
Start Bit
Verification
Yes
Yes
Yes
No
Yes
No
No
No
Noise Flag
0
1
1
0
1
0
0
0
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Communications Interface Module (SCI)
Technical Data
295