MC68HC708MP16 Datasheet, PDF (80/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Table 6-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
SP1
IX
INH
INH
IMM
DIR
EXT
IX2
SP2
IX1
SP1
IX
MSB
0
1
2
3
4
5
6
9E6
7
8
9
A
B
C
D
9ED
E
9EE
F
LSB
5
4
3
4
1
1
4
5
3
7
3
2
3
4
4
5
3
4
2
0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG
RTI
BGE SUB SUB SUB SUB SUB SUB SUB SUB
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
5
4
4
5
6
4
4
3
2
3
4
4
5
3
4
2
1 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS
BLT
CMP CMP CMP CMP CMP CMP CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
2 BRSET1 BSET1 BHI
3 DIR 2 DIR 2 REL
5
7
3
MUL
DIV
NSA
1 INH 1 INH 1 INH
2
DAA
1 INH
3
2
3
4
4
5
3
4
2
BGT SBC SBC SBC SBC SBC SBC SBC SBC
2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
9
3
2
3
4
4
5
3
4
2
3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI
BLE
CPX
CPX CPX CPX CPX
CPX CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
2
2
2
3
4
4
5
3
4
2
4 BRSET2 BSET2 BCC
LSR LSRA LSRX LSR
LSR
LSR
TAP
TXS
AND AND AND AND AND AND AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
3
4
3
5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM
4
1
2
2
3
4
4
5
3
4
2
CPHX TPA
TSX
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
2
6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH
2
3
4
4
5
3
4
2
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
2
1
2
3
4
4
5
3
4
2
7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX
AIS
STA
STA
STA
STA
STA
STA
STA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
2
1
2
3
4
4
5
3
4
2
8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL
LSL
LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
2
1
2
3
4
4
5
3
4
2
9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
2
2
2
3
4
4
5
3
4
2
A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC DEC PULH CLI
ORA ORA ORA ORA ORA ORA ORA ORA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
5
3
3
5
6
4
2
2
2
3
4
4
5
3
4
2
B BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI
ADD ADD ADD ADD ADD ADD ADD ADD
3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 4 SP1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
4
1
1
4
5
3
1
1
C BRSET6 BSET6 BMC INC INCA INCX INC
INC
INC CLRH RSP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH
2
3
4
JMP JMP JMP
2 DIR 3 EXT 3 IX2
3
JMP
2 IX1
2
JMP
1 IX
5
4
3
3
1
1
3
4
2
D BRCLR6 BCLR6 BMS
TST TSTA TSTX TST
TST
TST
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX
1
4
4
5
6
NOP BSR
JSR
JSR
JSR
1 INH 2 REL 2 DIR 3 EXT 3 IX2
5
JSR
2 IX1
4
JSR
1 IX
5
4
3
E BRSET7 BSET7 BIL
3 DIR 2 DIR 2 REL
5
4
4
MOV MOV MOV
3 DD 2 DIX+ 3 IMD
4
1
2
3
4
4
5
3
4
2
MOV STOP
2 IX+D 1 INH
*
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5
4
3
3
1
1
3
4
2
1
1
2
3
4
4
5
3
4
2
F BRCLR7 BCLR7 BIH
CLR CLRA CLRX CLR CLR CLR WAIT TXA
AIX
STX
STX STX
STX
STX
STX STX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
INH Inherent
REL Relative
IMM Immediate
IX Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
Low Byte of Opcode in Hexadecimal
MSB
LSB
0
0 High Byte of Opcode in Hexadecimal
5 Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode