MC68HC708MP16 Datasheet, PDF (310/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface Module (SCI)
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is automatically cleared when data, preamble or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when ten or eleven consecutive
logic 1s appear on the receiver input. IDLE generates an SCI error
CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the
IDLE bit by reading SCS1 with IDLE set and then reading the SCDR.
After the receiver is enabled, it must receive a valid character that sets
the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the
SCRF bit before an idle condition can set the IDLE bit. Reset clears
the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
Technical Data
310
MC68HC708MP16 — Rev. 3.1
Serial Communications Interface Module (SCI)
Freescale Semiconductor