MC68HC708MP16 Datasheet, PDF (242/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
12.9.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE:
If you read TBCNTH during a break interrupt, be sure to unlatch TBCNTL
by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
TBCNTH
$0040 Bit 7
6
Read: Bit 15
14
5
4
3
2
13
12
11
10
1
Bit 0
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
TBCNTL
$0041 Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-5. TIMB Counter Registers (TBCNTH:TBCNTL)
Technical Data
242
Timer Interface Module B (TIMB)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor