MC68HC708MP16 Datasheet, PDF (259/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 13.8.2 Mode Fault Error.) When CPHA = 0, the first SPSCK
edge is the MSB capture strobe. Therefore the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the slave data transmission. The slave’s SS pin must be
toggled back to high and then low again between each byte transmitted
as shown in Figure 13-5.
(FOSRPSRCEKFECRYECNLCEE#)
SPSCK (CPOL = 0)
1
2
3
4
5
6
7
8
SPSCK (CPOL =1)
(FROM MASMTEORS)I
(FROM SLMAIVSEO)
SS (TO SLAVE)
CAPTURE STROBE
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
Figure 13-4. Transmission Format (CPHA = 0)
MISO/MOSI
MASTER SS
SLAVE SS
(CPHA = 0)
SLAVE SS
(CPHA = 1)
BYTE 1
BYTE 2
BYTE 3
Figure 13-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
259