MC68HC708MP16 Datasheet, PDF (118/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See 8.4.3 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. (See 8.4.3
Base Clock Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT.
0 = CGMXCLK divided by two drives CGMOUT.
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See 8.4.3 Base Clock Selector Circuit.)
PCTL[3:0] — Unimplemented bits
These bits provide no function and always read as logic 1s.
Technical Data
118
Clock Generator Module (CGM)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor