MC68HC708MP16 Datasheet, PDF (233/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
PTEx/TCHxB
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 12-3. PWM Period and Pulse Width
OUTPUT
COMPARE
The value in the TIMB counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see 12.9.1 TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50%.
12.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 12.4.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIMB channel
registers.
An unsynchronized write to the TIMB channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMB overflow interrupt
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Timer Interface Module B (TIMB)
Technical Data
233