MC68HC708MP16 Datasheet, PDF (349/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
Addr.
$FE0F
Name
Bit 7 6
5
4
3
Read: LVIOUT 0
0
0
0
LVI Status Register
(LVISR)
Write:
Reset: 0
0
0
0
0
= Unimplemented
Figure 18-2. LVI I/O Register Summary
2
1 Bit 0
0
0
0
0
0
0
18.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the configuration
register, the LVIPWR bit must be at logic 0 to enable the LVI module, and
the LVIRST bit must be at logic 1 to disable LVI resets.
18.4.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls to the LVI_TRIPF level and remains at or below that level for nine or
more consecutive CPU cycles. In the configuration register, the LVIPWR
and LVIRST bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
18.4.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,V_DD must
remain at or below the LVI_TRIPF level for nine or more consecutive CPU
cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the
MCU out of reset.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
Technical Data
349