MC68HC708MP16 Datasheet, PDF (92/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
7.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
7.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-8 shows interrupt entry timing.
Figure 7-10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
(See Figure 7-9.)
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H VECT L START ADDR
DUMMY PC–1[7:0] PC–1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
Figure 7-8. Interrupt Entry
Technical Data
92
System Integration Module (SIM)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor