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MC68HC708MP16 Datasheet, PDF (162/398 Pages) Freescale Semiconductor, Inc – Microcontrollers
NON-DISCLOSURE AGREEMENT REQUIRED
CYCLE START
(LOGIC HIGH FOR FAULT)
FPIN1
FMODE1
FAULT
PIN1
TWO
SAMPLE
FILTER
ONE
SHOT
S
R
CLEAR BY WRITING 1 TO FTACK1
Q FFLAG1
AUTO
MODE
MANUAL
MODE
FINT1
FAULT PIN 1 DISABLE
SQ
R
BANK X DISABLE
INTERRUPT REQUEST
The example is of fault pin 1. Fault pin 3 is logically similar and effects BANK Y disable.
NOTE: In manual mode (FMODE = 0) fault 1 and 3 may be cleared regardless of the logic level at the input of the fault pin.
Figure 9-32. PWM Disabling Scheme (Sheet 2 of 2)