MC68HC708MP16 Datasheet, PDF (117/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.6.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, the base clock selector bit.
Address: $FE0B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PILLIE
PLLON BCS
Write:
Reset: 0
0
1
0
1
1
1
1
= Unimplemented
Figure 8-5. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
117