MC68HC708MP16 Datasheet, PDF (265/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the
SPRF, MODF, and OVRF interrupts share the same CPU interrupt
vector. (See Figure 13-11.) It is not possible to enable MODF or OVRF
individually to generate a receiver/error CPU interrupt request. However,
leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 13-9 shows how it is possible to
miss an overflow. The first part of Figure 13-9 shows how it is possible
to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ
2
5
SPSCR
READ
SPDR
3
1 BYTE 1 SETS SPRF BIT.
2 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 BYTE 2 SETS SPRF BIT.
7
5 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 13-9. Missed Read of Overflow Condition
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
265