MC68HC708MP16 Datasheet, PDF (104/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 124
8.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . 124
8.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . 126
8.10.3 Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . 127
8.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2 Introduction
This section describes the clock generator module (CGM, Version A).
The CGM generates the crystal clock signal, CGMXCLK, which operates
at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, from which the system integration module (SIM)
derives the system clocks. CGMOUT is based on either the crystal clock
divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided
by two. The PLL is a frequency generator designed for use with crystals
or ceramic resonators. The PLL can generate an 8-MHz bus frequency
without using a 32-MHz crystal.
8.3 Features
Features of the CGM include the following:
• Phase-locked loop with output frequency in integer multiples of the
crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
Technical Data
104
Clock Generator Module (CGM)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor