MC68HC708MP16 Datasheet, PDF (312/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface Module (SCI)
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 1)
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 2)
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 3)
BYTE 4
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 1)
BYTE 3
READ SCS1
SCRF = 1
OR = 1
READ SCDR
(BYTE 3)
BYTE 4
Figure 14-11. Flag Clearing Sequence
Technical Data
312
MC68HC708MP16 — Rev. 3.1
Serial Communications Interface Module (SCI)
Freescale Semiconductor