MC68HC708MP16 Datasheet, PDF (122/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
Table 8-1. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f_VRS. (See 8.4.2.1 PLL Circuits, 8.4.2.4 Programming the PLL, and
8.6.1 PLL Control Register.) VRS[7:4] cannot be written when the
PLLON bit in the PLL control register (PCTL) is set. (See 8.4.2.5
Special Programming Exceptions.) A value of $0 in the VCO range
select bits disables the PLL and clears the BCS bit in the PCTL. (See
8.4.3 Base Clock Selector Circuit and 8.4.2.5 Special
Programming Exceptions for more information.) Reset initializes
the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
Technical Data
122
Clock Generator Module (CGM)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor