MC68HC708MP16 Datasheet, PDF (177/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
NOTE: When PWMINT is cleared, pending CPU interrupts are inhibited.
DISX — Software Disable for Bank X
This read/write bit allows the user to disable one or more PWM pins
in bank X. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in bank X
0 = Re-enable PWM pins at beginning of next PWM cycle
DISY — Software Disable for Bank Y
This read/write bit allows the user to disable one or more PWM pins
in bank Y. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in bank Y
0 = Re-enable PWM pins at beginning of next PWM cycle
9.11.5 PWM Control Register 2
PWM control register 2 controls the PWM load frequency, the PWM
correction method, and the PWM counter prescaler. For ease of
software and to avoid erroneous PWM periods, some of these register
bits are buffered. The PWM generator will not use the prescaler value
until the LDOK bit has been set, and a new PWM cycle is starting. The
correction bits are used at the beginning of each PWM cycle (if the
ISENSx bits are configured for software correction). The load frequency
bits are not used until the current load cycle is complete.
NOTE: The user should initialize this register before enabling the PWM.
Address: $0021
Bit 7
6
5
4
3
2
1
Read:
0
LDFQ1 LDFQ0
IPOL1 IPOL2 IPOL3 PRSC1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 9-44. PWM Control Register 2 (PCTL2)
Bit 0
PRSC0
0
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
177