MC68HC708MP16 Datasheet, PDF (343/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
17.5 IRQ1/V_PP Pin
A logic 0 on the IRQ1/V_PP pin can latch an interrupt request into the
IRQ1 latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1/V_PP pin is both falling-edge-sensitive
and low-level-sensitive. With MODE1 set, both of the following actions
must occur to clear the IRQ1 latch:
• Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the latch. Software can
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ1/V_PP pin
and require software to clear the IRQ1 latch. Writing to the ACK1
bit can also prevent spurious interrupts due to noise. Setting ACK1
does not affect subsequent transitions on the IRQ1/V_PP pin. A
falling edge that occurs after writing to the ACK1 bit latches
another interrupt request. If the IRQ1 mask bit, IMASK1, is clear,
the CPU loads the program counter with the vector address at
locations $FFFA and $FFFB.
• Return of the IRQ1/V_PP pin to logic 1 — As long as the IRQ1/V_PP
pin is at logic 0, the IRQ1 latch remains set.
The vector fetch or software clear and the return of the IRQ1/V_PP pin to
logic 1 can occur in any order. The interrupt request remains pending as
long as the IRQ1/V_PP pin is at logic 0.
If the MODE1 bit is clear, the IRQ1/V_PP pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 latch.
NOTE:
Use the BIH or BIL instruction to read the logic level on the IRQ1/V_PP pin.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
External Interrupt (IRQ)
Technical Data
343