MC68HC708MP16 Datasheet, PDF (163/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
To allow for different motor configurations and the controlling of more
than one motor, the PWM disabling function is organized as two banks,
bank X and bank Y. Bank information combines with information from
the disable mapping register to allow selective PWM disabling. Fault pin
1, fault pin 2, and PWM disable bit X constitute the disabling function of
bank X. Fault pin 3, fault pin 4, and PWM disable bit Y constitute the
disabling function of bank Y. Figure 9-33 and Figure 9-34 show the
disable mapping write-once register and the decoding scheme of the
bank which selectively disables PWM(s). When all bits of the disable
mapping register are set, any disable condition will disable all PWMs.
A fault can also generate a CPU interrupt. Each fault pin has its own
interrupt vector.
Address: $0037
Bit 7
Read:
Write:
BIT 7
Reset: 1
6
5
4
3
2
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
1
1
1
1
1
Figure 9-33. PWM Disable Mapping
Write-Once Register (DISMAP)
1
BIT 1
1
Bit 0
BIT 0
1
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
163