MC68HC708MP16 Datasheet, PDF (275/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
MISO/MOSI
MASTER SS
SLAVE SS
(CPHA = 0)
SLAVE SS
(CPHA = 1)
BYTE 1
BYTE 2
BYTE 3
Figure 13-12. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See 13.14.2
SPI Status and Control Register.)
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-
impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See 13.8.2 Mode Fault Error.) For the state of the
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. (See
Table 13-3.)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
275