MC68HC708MP16 Datasheet, PDF (223/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module A (TIMA)
11.9.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
TACH0H
$0012 Bit 7
6
5
4
3
2
1
Bit 0
Read: _{Bit 15}
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
TACH0L
$0013 Bit 7
6
5
4
3
2
1
Bit 0
Read: _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
TACH1H
$0015 Bit 7
6
5
4
3
2
1
Bit 0
Read: _{Bit 15}
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
TACH1L
$0016 Bit 7
6
5
4
3
2
1
Bit 0
Read: _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 11-9. TIMA Channel Registers (TACH0H/L:TACH1H/L)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Timer Interface Module A (TIMA)
Technical Data
223