MC68HC708MP16 Datasheet, PDF (173/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
9.11.2 PWM Counter Modulo Registers
This PWM counter modulus register holds a 12-bit unsigned number that
determines the maximum count for the up/down or up-only counter. In
center-aligned mode, the PWM period will be twice the modulus
(assuming no prescaler). In edge-aligned mode, the PWM period will
equal the modulus.
PMODH
$0028 Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
11
10
9
BIT 8
Write:
Reset: 0
0
0
0
X
X
X
X
PMODL
$0029 Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reset: X
X
X
X
X
X
X
X
= Unimplemented
Figure 9-41. PWM Counter Modulo Registers (PDMODH:PMODL)
To avoid erroneous PWM periods, this value is buffered and will not be
used by the PWM generator until the LDOK bit has been set and the next
PWM load cycle begins.
NOTE: When reading this register, the value read is the buffer (not necessarily
the value the PWM generator is currently using).
CAUTION:
The user is responsible for initializing the PWM counter modulo registers
before enabling the PWM module. Since these registers are undefined
at reset, they could contain a combined value of $0000, which would
result in erroneous pulse widths. However, the dead-time constraints will
still be guaranteed, and the fault detection circuitry will still function
properly.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
173