MC68HC708MP16 Datasheet, PDF (345/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
17.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) has these functions:
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt requests
• Controls triggering sensitivity of the IRQ1/V_PP interrupt pin
Address: $001E
Read:
0
0
0
0
0
IRQ1F
IMASK1 MODE1
Write:
ACK1
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 17-4. IRQ Status and Control Register (ISCR)
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1
always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests.
Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1/V_PP
pin. Reset clears MODE1.
1 = IRQ1/V_PP interrupt requests on falling edges and low levels
0 = IRQ1/V_PP interrupt requests on falling edges only
IRQ1F — IRQ1 Flag
This read-only bit acts as a status flag, indicating an IRQ1 event
occurred.
1 = External IRQ1 event occurred
0 = External IRQ1 event did not occur
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
External Interrupt (IRQ)
Technical Data
345