MC68HC708MP16 Datasheet, PDF (213/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module A (TIMA)
11.7 TIMA During Break Interrupts
A break interrupt stops the TIMA counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 7.7.4 SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
11.8 I/O Signals
Port E shares three of its pins with the TIMA. PTE0/TCLKA is an external
clock input to the TIMA prescaler. The two TIMA channel I/O pins are
PTE1/TCH0A and PTE2/TCH1A.
11.8.1 TIMA Clock Pin (PTE0/TCLKA)
PTE0/TCLKA is an external clock input that can be the clock source for
the TIMA counter instead of the prescaled internal bus clock. Select the
PTE0/TCLKA input by writing logic 1s to the three prescaler select bits,
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Timer Interface Module A (TIMA)
Technical Data
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