MC68HC708MP16 Datasheet, PDF (335/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 13-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2¹⁸ – 2⁴ CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout
period is 53.3 ms. Writing any value to location $FFFF before overflow
occurs clears the COP counter and prevents reset.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see 7.7.3 SIM Reset
Status Register).
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
16.4 I/O Signals
The following paragraphs describe the signals shown in Figure 16-1.
16.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
16.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 16.5 COP
Control Register) clears the COP counter and clears bits 12 through 4
of the SIM counter. Reading the COP control register returns the reset
vector.
16.4.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096
CGMXCLK cycles after power-up.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Computer Operating Properly (COP)
Technical Data
335