MC68HC708MP16 Datasheet, PDF (348/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
18.4 Functional Description
Figure 18-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V_DD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V_DD falls below a voltage, LVI_TRIPF, and remains at or
below that level for nine or more consecutive CPU cycles. LVIPWR and
LVIRST are in the configuration register (CONFIG). (See Section 5.
Configuration Register (CONFIG).) Once an LVI reset occurs, the
MCU remains in reset until V_DD rises above a voltage, LVI_TRIPR. V_DD
must be above LVI_TRIPR for only one CPU cycle to bring the MCU out of
reset. (See 7.4.2.5 Low-Voltage Inhibit (LVI) Reset.) The output of the
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
DLEOTEWCVT^DO^DR
LVIPWR
FROM CONFIG
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
DIGITAVL^DDFILTER
FROM CONFIG
LVIRST
LVI RESET
ANLGTRIP
LVIOUT
Figure 18-1. LVI Module Block Diagram
Technical Data
348
Low-Voltage Inhibit (LVI)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor