MC68HC708MP16 Datasheet, PDF (235/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTE5/TCH1B, is available as a general-purpose I/O
pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTE6/TCH2B pin. The TIMB channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIMB channel 2 status and control register
(TBSC2) links channel 2 and channel 3. The TIMB channel 2 registers
initially control the pulse width on the PTE6/TCH2B pin. Writing to the
TIMB channel 3 registers enables the TIMB channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMB channel registers (2 or
3) that control the pulse width are the ones written to last. TBSC2
controls and monitors the buffered PWM function, and TIMB channel 3
status and control register (TBSC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTE7/TCH3B, is available as a general-purpose I/O
pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
12.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIMB status and control register (TBSC):
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter by setting the TIMB reset bit, TRST.
2. In the TIMB counter modulo registers (TBMODH:TBMODL), write
the value for the required PWM period.
3. In the TIMB channel x registers (TBCHxH:TBCHxL), write the
value for the required pulse width.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Timer Interface Module B (TIMB)
Technical Data
235