MC68HC708MP16 Datasheet, PDF (360/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
19.8.1 ADC Status and Control Register
These paragraphs describe the function of the ADC status and control
register (ADSCR).
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read: _COCO/
Write: ^IDMAS
AIEN
ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Reset: 0
0
0
0
0
0
0
0
Figure 19-2. ADC Status and Control Register (ADSCR)
COCO/IDMAS — Conversions Complete / Interrupt DMA Select
When AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit which
is set each time a conversion is completed except in the continous
conversion mode where it is set after the first conversion. This bit is
cleared whenever the ADC status and control register is written or
whenever the ADC data register is read.
If AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request.
Reset clears this bit.
1 = Conversion completed (AIEN = 0)/DMA interrrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)
AIEN — ADC Interrupt Enable
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
Technical Data
360
Analog-to-Digital Converter (ADC)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor