MC68HC708MP16 Datasheet, PDF (363/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
19.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address: $0019
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-3. ADC Data Register (ADR)
19.8.3 ADC Clock Register
This register selects the clock frequency for the ADC.
Address: $001A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
ADIV2 ADIV1 ADIV0 ADCLK
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-4. ADC Clock Register (ADCLKR)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 19-2 shows the available clock configurations. The ADC clock
should be set to 1 MHz.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Technical Data
363