S9S12XS256J0CAL Datasheet, PDF (93/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Field
7-0
PTIS
Table 2-24. PTIS Register Field Descriptions
Description
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.28 Port S Data Direction Register (DDRS)
Address 0x0249
R
W
Reset
7
DDRS7
0
1 _{Read: Anytime}
Write: Anytime
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 2-26. Port S Data Direction Register (DDRS)
Access: User read/write¹
1
0
DDRS1
DDRS0
0
0
Table 2-25. DDRS Register Field Descriptions
Field
7-4
DDRS
Description
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
3-2
DDRS
1 Associated pin configured as output
0 Associated pin configured as input
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI1 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1-0
DDRS
1 Associated pin configured as output
0 Associated pin configured as input
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
93