S9S12XS256J0CAL Datasheet, PDF (725/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Detailed Register Address Map
Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name
R
0xXX1F CANxTTSRL
W
Bit 7
TSR7
Bit 6
TSR6
Bit 5
TSR5
Bit 4
TSR4
Bit 3
TSR3
Bit 2
TSR2
Bit 1
TSR1
0x0180–0x023F Reserved Register Space
Address Name
Bit 7
0x0180-
0x023F
R
Reserved
W
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
TSR0
Bit 0
0
0x0240–0x027F Port Integration Module (PIM) Map 5 of 5
Address
0x0240
0x0241
0x0242
0x0243
0x0244
0x0245
0x0246
0x0247
Name
PTT
PTIT
DDRT
RDRT
PERT
PPST
Reserved
PTTRR
Bit 7
R
PTT7
W
R PTIT7
W
R
DDRT7
W
R
RDRT7
W
R
PERT7
W
R
PPST7
W
R
0
W
R
PTTRR7
W
Bit 6
PTT6
PTIT6
DDRT6
RDRT6
PERT6
PPST6
0
PTTRR6
Bit 5
PTT5
PTIT5
DDRT5
RDRT5
PERT5
PPST5
0
PTTRR5
Bit 4
PTT4
PTIT4
DDRT4
RDRT4
PERT4
PPST4
0
PTTRR4
Bit 3
PTT3
PTIT3
DDRT3
RDRT3
PERT3
PPST3
0
0
Bit 2
PTT2
PTIT2
Bit 1
PTT1
PTIT1
Bit 0
PTT0
PTIT0
DDRT2 DDRT1 DDRT0
RDRT2 RDRT1 RDRT0
PERT2 PERT1 PERT0
PPST2
0
PPST1
0
PPST0
0
PTTRR2 PTTRR1 PTTRR0
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
725