S9S12XS256J0CAL Datasheet, PDF (85/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Table 2-15. DDRK Register Field Descriptions
Field
7,5-0
DDRK
Description
Port K Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.3.18 Port T Data Register (PTT)
Address 0x0240
7
R
PTT7
W
6
PTT6
5
PTT5
4
PTT4
3
PTT3
2
PTT2
Altern.
Function
IOC7
(PWM7)
IOC6
(PWM6)
IOC5
(PWM5)
IOC4
(PWM4)
IOC3
—
IOC2
—
—
—
VREG_API
—
—
—
Reset
0
0
0
0
0
0
Figure 2-16. Port T Data Register (PTT)
1 _{Read: Anytime, the data source depends on the data direction value}
Write: Anytime
Access: User read/write¹
1
0
PTT1
PTT0
IOC1
—
—
0
IOC0
—
—
0
Table 2-16. PTT Register Field Descriptions
Field
7-6, 4
PTT
Description
Port T general purpose input/output data—Data Register, TIM output, routed PWM output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The TIM output function takes precedence over the routed PWM and the general purpose I/O function if the
related channel is enabled.
• The routed PWM function takes precedence over the general purpose I/O function if the related channel is
enabled.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
85