S9S12XS256J0CAL Datasheet, PDF (256/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV1)
8.4.1.2 System Clocks Generator
PLLSEL or SCM
PHASE
PLLCLK
1
LOCK
LOOP (IIPLL)
0
STOP
SYSCLK
Core Clock
EXTAL
OSCCLK
OSCILLATOR
XTAL
Clock
Monitor
SCM
1
0
WAIT(RTIWAI),
STOP(PSTP, PRE),
RTI ENABLE
WAIT(COPWAI),
STOP(PSTP, PCE),
COP ENABLE
÷2
CLOCK PHASE
GENERATOR
RTI
COP
Bus Clock
Gating
Condition
= Clock Gate
STOP
Oscillator
Clock
Figure 8-16. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 8-16). The gating condition placed on
top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see Section 8.4.2.2, “Self Clock Mode”) Oscillator clock source is switched
to PLLCLK running at its minimum frequency f_SCM. The Bus Clock is used to generate the clock visible
at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus Clock.
But note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.
S12XS Family Reference Manual, Rev. 1.13
256
Freescale Semiconductor