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S9S12XS256J0CAL Datasheet, PDF (586/738 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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128 KByte Flash Module (S12XFTMR128K1V1)
19.4.1.2 Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 19.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
19.4.1.2.1 Deï¬ne FCCOB Contents
The FCCOB parameter ï¬elds must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter ï¬elds is controlled via the CCOBIX bits in the FCCOBIX
register (see Section 19.3.2.3).
The contents of the FCCOB parameter ï¬elds are transferred to the Memory Controller when the user clears
the CCIF command completion ï¬ag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF ï¬ag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
return CCIF to 1 and the FCCOB register will be used to communicate any results. The ï¬ow for a generic
command write sequence is shown in Figure 19-26.
S12XS Family Reference Manual, Rev. 1.13
586
Freescale Semiconductor
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