S9S12XS256J0CAL Datasheet, PDF (108/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
2.3.49 Port P Interrupt Flag Register (PIFP)
Address 0x025F
R
W
Reset
7
PIFP7
0
1 _{Read: Anytime}
Write: Anytime
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
0
0
0
0
0
Figure 2-47. Port P Interrupt Flag Register (PIFP)
Access: User read/write¹
1
0
PIFP1
PIFP0
0
0
Field
7-0
PIFP
Table 2-46. PIFP Register Field Descriptions
Description
Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.3.50 Port H Data Register (PTH)
Address 0x0260
7
R
PTH7
W
6
PTH6
5
PTH5
4
PTH4
3
PTH3
2
PTH2
Reset
0
0
0
0
0
0
Figure 2-48. Port H Data Register (PTH)
1 _{Read: Anytime, the data source depends on the data direction value}
Write: Anytime
Access: User read/write¹
1
0
PTH1
PTH0
0
0
Field
7-0
PTH
Table 2-47. PTH Register Field Descriptions
Description
Port H general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
S12XS Family Reference Manual, Rev. 1.13
108
Freescale Semiconductor