S9S12XS256J0CAL Datasheet, PDF (112/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
2.3.57 Port H Interrupt Flag Register (PIFH)
Address 0x0267
R
W
Reset
7
PIFH7
0
1 _{Read: Anytime}
Write: Anytime
6
PIFH6
5
PIFH5
4
PIFH4
3
PIFH3
2
PIFH2
0
0
0
0
0
Figure 2-55. Port H Interrupt Flag Register (PIFH)
Access: User read/write¹
1
0
PIFH1
PIFH0
0
0
Field
7-0
PIFH
Table 2-54. PIFH Register Field Descriptions
Description
Port H interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.3.58 Port J Data Register (PTJ)
Address 0x0268
7
6
5
4
3
2
R
0
0
0
0
PTJ7
PTJ6
W
Reset
0
0
0
0
0
0
Figure 2-56. Port J Data Register (PTJ)
1 _{Read: Anytime, the data source depends on the data direction value}
Write: Anytime
Access: User read/write¹
1
0
PTJ1
PTJ0
0
0
Table 2-55. PTJ Register Field Descriptions
Field
Description
7-6, 1-0
PTJ
Port J general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
S12XS Family Reference Manual, Rev. 1.13
112
Freescale Semiconductor