S9S12XS256J0CAL Datasheet, PDF (237/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8
S12XE Clocks and Reset Generator (S12XECRGV1)
Table 8-1. Revision History
Revision
Number
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
Revision
Date
26 Oct. 2005
02 Nov 2006
4 Mar. 2008
1 Sep. 2008
20 Nov. 2008
19. Sep 2009
V01.06 18. Sep 2012
Sections
Affected
8.4.1.1/8-254
8.4.1.4/8-257
8.4.3.3/8-261
Table 8-14
8.3.2.4/8-243
8.5.1/8-263
Table 8-14
8.5.1
Description of Changes
Initial release
Table “Examples of IPLL Divider settings”: corrected $32 to $31
Corrected details
added 100MHz example for PLL
S12XECRG Flags Register: corrected address to Module Base + 0x0003
Modified Note below Table 8-17./8-263
Added footnote concerning maximum clock frequencies to table
Removed redundant examples from table
Replaced reference to MMC documentation
8.1 Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
8.1.1 Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
• System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
• Computer Operating Properly (COP) watchdog timer with time-out clear window.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
237