S9S12XS256J0CAL Datasheet, PDF (83/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.14 IRQ Control Register (IRQCR)
Port Integration Module (S12XSPIMV1)
Address 0x001E
7
6
5
4
3
2
R
0
0
0
0
IRQE
IRQEN
W
Reset
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 2-12. IRQ Control Register (IRQCR)
1 _{Read: See individual bit descriptions below}
Write: See individual bit descriptions below
Access: User read/write¹
1
0
0
0
0
0
Table 2-13. IRQCR Register Field Descriptions
Field
7
IRQE
IRQ select edge sensitive only—
Special mode: Read or write anytime
Normal mode: Read anytime, write once
Description
6
IRQEN
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ configured for low level recognition.
IRQ enable—
Read or write anytime
1 IRQ pin is connected to interrupt logic.
0 IRQ pin is disconnected from interrupt logic.
2.3.15 PIM Reserved Register PIMTEST¹
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Writing to this register when in special modes can alter the pin functionality.
Address 0x001F
Access: User read¹
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-13. PIM Reserved Register
1. Implementation pim_xe.01.01 and later
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
83