S9S12XS256J0CAL Datasheet, PDF (51/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device Overview S12XS Family
1.4.2.5 Run Mode
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.4.3 Freeze Mode
The timer module, pulse width modulator, analog-to-digital converters, and the periodic interrupt timer
provide a software programmable option to freeze the module status when the background debug module
is active. This is useful when debugging application software. For detailed description of the behavior of
the ATD, TIM, PWM, and PIT when the background debug module is active consult the corresponding
section.
1.5 Security
The MCU security mechanism prevents unauthorized access to the Flash memory. For a detailed
description of the security features refer to the S12XS9SEC section.
1.6 Resets and Interrupts
Consult the CPU12/CPU12X Reference Manual and the S12XINT section for information on exception
processing.
NOTE
When referring to the S12XINT section please be aware that the XS family
neither features an XGATE nor an MPU module.
1.6.1 Resets
Resets are explained in detail in the Clock Reset Generator (S12XECRG) section.
Table 1-9. Reset Sources and Vector Locations
Vector Address
Reset Source
CCR
Mask
Local Enable
$FFFE
$FFFE
$FFFE
$FFFE
$FFFC
$FFFA
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock monitor reset
COP watchdog reset
None
None
None
None
None
None
None
None
None
None
PLLCTL (CME, SCME)
COP rate select
1.6.2 Vectors
Table 1-10 lists all interrupt sources and vectors in the default order of priority. The interrupt module
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
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