S9S12XS256J0CAL Datasheet, PDF (349/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12
Periodic Interrupt Timer (S12PIT24B4CV1)
Table 12-1. Revision History
Version Revision Effective
Number Date
Date
01.00 28-Apr-05 28-Apr-05
01.01 05-Jul-05 05-Jul-05
Author
Description of Changes
Initial Release
Added application section, removed table 1-1
12.1 Introduction
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to Figure 12-1 for a simplified block diagram.
12.1.1 Glossary
PIT
ISR
CCR
SoC
micro time bases
Acronyms and Abbreviations
Periodic Interrupt Timer
Interrupt Service Routine
Condition Code Register
System on Chip
clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.
12.1.2 Features
The PIT includes these features:
• Four timers implemented as modulus down-counters with independent time-out periods.
• Time-out periods selectable between 1 and 2²⁴ bus clock cycles. Time-out equals m*n bus clock
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
• Timers that can be enabled individually.
• Four time-out interrupts.
• Four time-out trigger output signals available to trigger peripheral modules.
• Start of timer channels can be aligned to each other.
12.1.3 Modes of Operation
Refer to the SoC guide for a detailed explanation of the chip modes.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
349