S9S12XS256J0CAL Datasheet, PDF (254/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12XE Clocks and Reset Generator (S12XECRGV1)
8.4 Functional Description
8.4.1 Functional Blocks
8.4.1.1 Phase Locked Loop with Internal Filter (IPLL)
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 8-15
shows a block diagram of the IPLL.
EXTAL
XTAL
REDUCED
CONSUMPTION ^OSCCLK
OSCILLATOR
REFDIV[5:0]
REFCLK
FBCLK
LOCK
DETECTOR
LOCK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
V_DDPLL/V_SSPLL
UP _CPUMP
DOWN ^AND
VCO
FILTER
CLOCK
MONITOR
Supplied by:
V_DDPLL/V_SSPLL
V_DD/V_SS
LOOP
PROGRAMMABLE
DIVIDER
SYNDIV[5:0]
VCOCLK
POST
PROGRAMMABLE
DIVIDER
POSTDIV[4:0]
PLLCLK
Figure 8-15. IPLL Functional Diagram
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
.
f _PLL = 2 × f _OSC × _[---_R----_E----_F---_D-----_I--_V--^S----^Y₊----^N-₁---_]-^D--_[--_2I---^V--_×---⁺-_P----_O1-----_S---_T----_D-----_I--_V-----_]
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1) then f_BUS = f_PLL / 2.
IF POSTDIV = $00 the f_PLL is identical to f_VCO (divide by one)
Several examples of IPLL divider settings are shown in Table 8-14. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
• Use lowest possible f_VCO / f_REF ratio (SYNDIV value).
• Use highest possible REFCLK frequency f_REF.
S12XS Family Reference Manual, Rev. 1.13
254
Freescale Semiconductor