S9S12XS256J0CAL Datasheet, PDF (45/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device Overview S12XS Family
1.2.3.36 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 0 (SCI0).
1.2.3.37 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 0 (SCI0).
1.2.3.38 PT[7:6] / IOC[7:6] / PWM[7:6] — Port T I/O Pins 7-6
PT[7:6] are general-purpose input or output pins. They can be configured as timer (TIM) channel 7-6 or
pulse width modulator (PWM) outputs 7-6
1.2.3.39 PT5 / IOC5 / VREG_API — Port T I/O Pin 5
PT[5] is a general-purpose input or output pin. It can be configured as timer (TIM) channel 5, pulse width
modulator (PWM) output 5 or as the VREG_API signal output.
1.2.3.40 PT4 / IOC4 / PWM4 — Port T I/O Pin 4
PT4 is a general-purpose input or output pin. It can be configured as timer (TIM) channel 4 or pulse width
modulator (PWM) output 4.
1.2.3.41 PT[3:0] / IOC[3:0] — Port T I/O Pin [3:0]
PT[3:0] are a general-purpose input or output pins. They can be configured as timer (TIM) channels 3-0.
1.2.4 Power Supply Pins
S12XS Family power and ground pins are described below.
Because fast signal transitions place high, short-duration current demands on the power supply, use bypass
capacitors with high-frequency characteristics and place them as close to the MCU as possible.
NOTE
All V_SS pins must be connected together in the application.
1.2.4.1 VDDX[2:1], VSSX[2:1] — Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded. All V_DDX pins are connected together internally. All V_SSX pins are connected together internally.
1.2.4.2 VDDR — Power Pin for Internal Voltage Regulator
Power supply input to the internal voltage regulator.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
45