S9S12XS256J0CAL Datasheet, PDF (116/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
2.3.65 Port J Interrupt Flag Register (PIFJ)
Address 0x026F
R
W
Reset
7
PIFJ7
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
PIFJ6
0
0
0
0
0
Figure 2-63. Port J Interrupt Flag Register (PIFJ)
Access: User read/write¹
1
0
PIFJ1
PIFJ0
0
0
Table 2-62. PIFJ Register Field Descriptions
Field
Description
7-6, 1-0
PIFJ
Port J interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.3.66 Port AD0 Data Register 0 (PT0AD0)
Address 0x0270
7
R
PT0AD07
W
6
PT0AD06
5
PT0AD05
4
PT0AD04
3
PT0AD03
2
PT0AD02
Altern.
Function
AN15
AN14
AN13
AN12
AN11
AN10
Reset
0
0
0
0
0
0
Figure 2-64. Port AD0 Data Register 0 (PT0AD0)
1 _{Read: Anytime, the data source depends on the data direction value}
Write: Anytime
Access: User read/write¹
1
0
PT0AD01 PT0AD00
AN9
AN8
0
0
Table 2-63. PT0AD0 Register Field Descriptions
Field
Description
7-0
PT0AD0
Port AD0 general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
S12XS Family Reference Manual, Rev. 1.13
116
Freescale Semiconductor