S9S12XS256J0CAL Datasheet, PDF (126/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Table 2-72. Pulse Detection Criteria
Mode
Pulse
STOP
STOP¹
Unit
Ignored
t_pulse ≤ 3 bus clocks
t_pulse ≤ t_pign
Uncertain
3 < t_pulse < 4 bus clocks
t_pign < t_pulse < t_pval
Valid
t_pulse ≥ 4 bus clocks
t_pulse ≥ t_pval
1_{These values include the spread of the oscillator frequency over tempera-}
ture, voltage and process.
t_pulse
Figure 2-75. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
2.5 Initialization Information
2.5.1 Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
S12XS Family Reference Manual, Rev. 1.13
126
Freescale Semiconductor