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S9S12XS256J0CAL Datasheet, PDF (147/738 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Memory Mapping Control (S12XMMCV4)
3.4.3 Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM )
with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping
operations. All internal resources are connected to speciï¬c target buses (see Figure 3-20).
MMC
BDM
S12X1
Address Decoder & Priority
CPU
S12X0
DBG
Target Bus Controller
XBUS0
Data FLASH PGMFLASH
RAM
Peripherals
Figure 3-20. MMC Block Diagram
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
147
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