S9S12XS256J0CAL Datasheet, PDF (695/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Characteristics
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
1
2
4
4
5
6
MSB IN2
9
MOSI
(Output)
Port Data
Master MSB OUT2
12
12
Bit MSB-1. . . 1
11
Bit MSB-1. . . 1
13
3
13
LSB IN
Master LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure A-7. SPI Master Timing (CPHA = 1)
In Table A-27 the timing characteristics for master mode are listed.
Table A-27. SPI Master Mode Timing Characteristics
Num C
Characteristic
1
D SCK frequency
1
D SCK period
2
D Enable lead time
3
D Enable lag time
4
D Clock (SCK) high or low time
5
D Data setup time (inputs)
6
D Data hold time (inputs)
9
D Data valid after SCK edge
10
D Data valid after SS fall (CPHA = 0)
11
D Data hold time (outputs)
12
D Rise and fall time inputs
13
D Rise and fall time outputs
1^{See Figure A-8.}
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
20
—
t_rfi
—
—
t_rfo
—
—
Port Data
Max
1/2¹
2048
—
—
—
—
—
29
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
695