S9S12XS256J0CAL Datasheet, PDF (73/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0275 R
RDR1AD0 _W ^{RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00}
0x0276 R
PER0AD0 _W ^{PER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00}
0x0277 R
PER1AD0 _W ^{PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00}
0x0278 R
0
0
0
0
0
0
0
0
Reserved _W
0x0279 R
0
0
0
0
0
0
0
0
Reserved _W
0x027A R
0
0
0
0
0
0
0
0
Reserved _W
0x027B R
0
0
0
0
0
0
0
0
Reserved _W
0x027C R
0
0
0
0
0
0
0
0
Reserved _W
0x027D R
0
0
0
0
0
0
0
0
Reserved _W
0x027E R
0
0
0
0
0
0
0
0
Reserved _W
0x027F R
0
0
0
0
0
0
0
0
Reserved _W
= Unimplemented or Reserved
2.3.2 Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt enabled.
2. Select either a pull-up or pull-down device if PE is active.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
73