S9S12XS256J0CAL Datasheet, PDF (280/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC12B16CV1)
Table 10-6. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
1
0
0
1
0
1
0
0
1
1
ETRIG2¹
ETRIG3¹
1
0
1
X
X
Reserved
1
1
X
X
X
Reserved
1 _{Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means}
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
10.3.2.3 ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Module Base + 0x0002
7
R
0
W
6
AFFC
5
ICLKSTP
4
ETRIGLE
3
ETRIGP
2
ETRIGE
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-6. ATD Control Register 2 (ATDCTL2)
Read: Anytime
Write: Anytime
Table 10-7. ATDCTL2 Field Descriptions
1
ASCIE
0
0
ACMPIE
0
Field
Description
6
AFFC
5
ICLKSTP
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
Internal Clock in Stop Mode Bit — This bit enables A/D conversions in stop mode. When going into stop mode
and ICLKSTP=1 the ATD conversion clock is automatically switched to the internally generated clock ICLK.
Current conversion sequence will seamless continue. Conversion speed will change from prescaled bus
frequency to the ICLK frequency (see ATD Electrical Characteristics in device description). The prescaler bits
PRS4-0 in ATDCTL4 have no effect on the ICLK frequency. For conversions during stop mode the automatic
compare interrupt or the sequence complete interrupt can be used to inform software handler about changing
A/D values. External trigger will not work while converting in stop mode. For conversions during transition from
Run to Stop Mode or vice versa the result is not written to the results register, no CCF flag is set and no compare
is done. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time t_ATDSTPRCV is required to
switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
0 If A/D conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be
aborted and automatically restarted when exiting stop mode.
1 A/D continues to convert in stop mode using internally generated clock (ICLK)
S12XS Family Reference Manual, Rev. 1.13
280
Freescale Semiconductor