S9S12XS256J0CAL Datasheet, PDF (288/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC12B16CV1)
Module Base + 0x0008
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CMPE[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-11. ATD Compare Enable Register (ATDCMPE)
Table 10-18. ATDCMPE Field Descriptions
Field
Description
15–0 Compare Enable for Conversion Number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence
CMPE[15:0] — These bits enable automatic compare of conversion results individually for conversions of a sequence. The
sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register.
For each conversion number with CMPE[n]=1 do the following:
1) Write compare value to ATDDRn result register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
CCF[n] in ATDSTAT2 register will flag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
S12XS Family Reference Manual, Rev. 1.13
288
Freescale Semiconductor