S9S12XS256J0CAL Datasheet, PDF (501/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

17.3.2.6 Reserved 06
The Reserved 06 is reserved for test purposes.
0x02F6
7
6
5
4
3
R
0
0
0
0
0
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-7. Reserved 06
Voltage Regulator (S12VREGL3V3V1)
2
1
0
0
0
0
0
0
0
17.3.2.7 High Temperature Trimming Register (VREGHTTR)
The VREGHTTR register allows to trim the VREG temperature sense.
Fiption
0x02F7
7
6
5
4
3
2
R
0
0
0
HTOEN
HTTR3
HTTR2
W
Reset
0
0
0
0
0¹
0¹
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
= Unimplemented or Reserved
Figure 17-8. VREGHTTR
1
HTTR1
0¹
0
HTTR0
0¹
Table 17-11. VREGHTTR field descriptions
Field
Description
7
HTOEN
3–0
HTTR[3:0]
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
High Temperature Trimming Bits — See Table 23-16 for trimming effects.
Bit
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
Table 17-12. Trimming Effect
Trimming Effect
Increases V_HT twice of HTTR[2]
Increases V_HT twice of HTTR[1]
Increases V_HT twice of HTTR[0]
Increases V_HT (to compensate Temperature Offset)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
501